• Hands on experience with FPGA design tools: Simplify, Vivado, XILINX ISE,
• Work experience in Xilinx FPGA based design implementation.
• FPGA RTL coding(Verilog/VHDL/System Verilog), FPGA constraint setup, verification, synthesis, par and timing closure.
• Hands-on experience in WIFI/Ethernet/PCIe/USB/Multimedia/UFS/ARM CPU/DDR3/DDR emulation.
• Familiar with hardware schematics and Lab tools to debug.
• Interact with software/Verification team to resolve FPGA related technical implementation and integration issues.
• Work closely with other RTL Design/Validation and Software teams for bug/issue debug, support and build bring up in emulation platform.